In the fabrication of semiconductor components, various devices are formed in layers upon an underlying substrate that is typically composed of a semiconductor material, such as silicon. The various discrete devices are interconnected by metal conductor lines to form the desired integrated circuits. The metal conductor lines are further insulated from the next interconnection level by thin films of insulating material deposited by, for example, CVD (Chemical Vapor Deposition) of oxide or application of SOG (Spin On Glass) layers followed by fellow processes. Holes, or vias, formed through the insulating layers provide electrical connectivity between successive conductive interconnection layers. In such microcircuit wiring processes, it is desirable that the insulating layers have a smooth surface topography, since it is difficult to lithographically image and pattern layers applied to rough surfaces.
Conventional chemical/mechanical polishing (CMP) has been developed for providing smooth semiconductor topographies. Chemical/mechanical polishing (CMP) can be used for planarizing: (a) insulator surfaces, such as silicon oxide or silicon nitride, deposited by chemical vapor deposition; (b) insulating layers, such as glasses deposited by spin-on and reflow deposition means, over semiconductor devices; or (c) metallic conductor interconnection wiring layers. Semiconductor wafers may also be planarized to: control layer thickness, sharpen the edge of via "plugs", remove a hardmask, remove other material layers, etc. Significantly, a given semiconductor wafer may be planarized several times, such as upon completion of each metal layer. For example, following via formation in a dielectric material layer, a metalization layer is blanket deposited and then CMP is used to produce planar metal studs.
Briefly, the CMP process involves holding and rotating a thin, reasonably flat, semiconductor wafer against a rotating polishing surface. The polishing surface is wetted by a chemical slurry, under controlled chemical, pressure, and temperature conditions. The chemical slurry contains a polishing agent, such as alumina or silica, which is used as the abrasive material. Additionally, the slurry contains selected chemicals which etch or oxidize selected surfaces of the wafer during processing. The combination of mechanical and chemical removal of material during polishing results in superior planarization of the polished surface. In this process it is important to remove a sufficient amount of material to provide a smooth surface, without removing an excessive amount of underlying materials. Accurate material removal is particularly important in today's submicron technologies where the layers between device and metal levels are constantly getting thinner.
One problem area associated with chemical/mechanical polishing is in the step of removing the planarized wafer from the wafer carrier in which it is held for polishing without damaging the wafer. The wafers are temporarily stored in deionized (DI) water while awaiting CMP or further processing. With the inner face of the wafer carrier wetted by DI water and the semiconductor wafer in contact with the inner face, the DI water creates a capillary adhesion force between the semiconductor wafer and the wafer carrier. As the CMP process proceeds, all gases, e.g., air, are expelled from between the wafer and the wafer carrier inner face. The resultant effect is the formation by adsorption of a thin film between the surface of the wafer carrier and the surface of the wafer. The DI water film adheres to the surfaces of both the semiconductor wafer and the wafer carrier. Thus, when the CMP process is complete and the wafer is to be returned to a storage location, the semiconductor wafer clings to the wafer carrier. It is necessary to break the seal between the wafer and the wafer carrier without damaging the wafer. Conventional eight inch wafer carriers, such as those associated with a SpeedFam polisher tool #9206) have two fluid draining grooves of approximately 0.25" width in a cruciform pattern about the center of the cup. Thus, the relieved area in which adhesion cannot occur is about eight percent (.about.4 in.sup.2 /.about.50 in.sup.2 =0.08) of the total cup surface area. Experience has shown that this configuration requires excessive force to "break" the adhesion between the wafer and the wafer carrier, resulting in wafer breakage. This is, of course, highly undesirable because of the cost associated with the lost production cost associated with such breakage.
Accordingly, what is needed in the art is an improved wafer carrier design that minimizes semiconductor wafer breakage while reducing unload cycle time.